1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width and indicating an execution state of a write command.
2. Description of the Background Art
FIG. 6 is a block diagram illustrating a structure of a conventional nonvolatile semiconductor memory device 101 (hereinafter referred to as a memory device 101) and its host system 102. The memory device 101 comprises: a memory cell array in which nonvolatile memory cells such as flash memory cells are disposed in the form of a matrix; and a control circuit therefor (both are not shown in the drawing). The control circuit comprises a circuit (e.g., a decoder, a sense amplifier, or a status register) for performing a write operation and a read operation based on a command outputted from the host system 102.
While writing is performed, a control signal (a chip enable signal NCE, an output enable signal NOE, and a write enable signal NWE), an address signal AIN, and a data signal DI are inputted to the memory device 101. These signals are outputted from the host system 102. Based on the inputted signals, the memory device 101 performs a series of processes including erasure, writing, and status signal output.
FIG. 7 is a timing chart showing a timing at which data is written into the conventional nonvolatile semiconductor memory device compliant with the JEDEC (Joint Electron Device Engineering Council) standard (more specifically, a timing at which a write command is executed and status check is performed). Note that the JEDEC standard-based nonvolatile semiconductor memory device is described in JEDEC Standard No 21-C, page 3.5.3-2. As shown in FIG. 7, according to the JEDEC standard, there are first to fourth cycles for each address command and data command used when data PD is written into an address PA. That is, four address commands (555, AAA, 555, and PA) and four data commands (AA, 55, A0, and PD) are sequentially inputted to the memory device 101. The first and second cycles (address commands 555 and AAA, and data commands AA and 55) correspond to a malfunction prevention cycle, which is referred to as an unlock cycle. Also, the third cycle (address commands 555 and data command A0) is a write setup cycle.
FIG. 7, DATA[7] and DATA[6] are 2-bit data contained in an 8-bit status signal indicating an execution state of a write command. DATA[7] and DATA[6] are read by the host system 102 via a cache memory 103, a multiplexer 104, and an 8-bit input-output data bus DB (more specifically, DB7 and DB6).
The memory device 101 has functions for data polling and toggle bit. These functions allow the host system 102 to read a status during writing or a status at the time of completion of writing. DATA[7] is a signal for data polling. As shown in FIG. 7, DATA [7] indicates the same value as that of data /DI7, which is inverted data of write data DI7, while writing is performed. When writing is completed, DATA [7] indicates the same value as that of write data DI7. On the other hand, DATA[6] is a signal which toggles with a chip enable signal NCE during writing and stops toggling when writing is completed. The host system 102 uses DATA[7] and DATA[6] outputted from the memory device 101 for performing status check.
Conventionally, the use of a memory device whose output data width is wider than an input data width requires address control for status check. For example, the memory device 101 as shown in FIG. 6 performs address control so that a status signal is outputted from lower 8 bits of 64-bit output, and the status signal thus outputted is inputted to the host system 102 via the 8-bit input-output data bus DB. Therefore, when writing is performed for an address whose lower 3 bits are other than zero, it is necessary to perform address control for changing the lower 3 bits of the address to 0 h. In order to perform such address control, it is necessary to design appropriate software to be installed in the host system, or additionally provide hardware such as an address decoding circuit.
However, the complexity of the conventional address control contributes to the increased number of processes for software development or bloated software. Also, due to the necessity of the above-described address control, the conventional memory device needs to be combined with a particular host system, whereby the usability of the device is impaired.